SoC Interconnect & Memory ASIC Engineer

QUALCOMM, Inc.; San Diego (CA); Vor Ort; USD 101.000 - 152.000; Vollzeit

Zusammenfassung

Qualcomm Technologies, Inc. in San Diego seeks ASIC Design Engineers to contribute to architecture, microarchitecture, and RTL for high‑performance SoC interconnects and memory controllers.

You will work with architecture, verification, and physical design teams to deliver power‑efficient silicon across product cycles and collaborate on C/C++ modeling and RTL workflows. The role emphasizes design quality, timing closure, and cross‑functional collaboration in a fast-paced hardware environment

Qualifikationen

• Experience with Verilog/SystemVerilog RTL design.
• Background in Computer Architecture and ASIC design methodologies.
• Proficiency in C/C++ or Python programming for modeling and tooling.
• Strong analytical and communication skills.

Aufgaben

• Develop microarchitecture definitions and design specifications for complex SoC subsystems.
• Design, implement, and validate RTL for interconnects, cache controllers, memory subsystems, and DDR controllers.
• Collaborate with system architects to evaluate hardware feasibility of new features and performance requirements.
• Optimize designs for performance, power, area, timing, and scalability.
• Work with verification teams to develop test plans, review coverage, and debug issues.
• Support synthesis, timing closure, power analysis, gate-level simulations, and physical design activities.
• Participate in system-level integration and debugging throughout the product development cycle.
• Investigate and resolve pre-silicon and post-silicon issues.
• Contribute to C/C++ modeling, design methodologies, and process improvements.

Kenntnisse

Verilog/SystemVerilog

Computer Architecture

C/C++/Python programming

Digital logic design

Ausbildung

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

Synopsys synthesis tools

Jobbeschreibung

Qualcomm Technologies, Inc. in San Diego seeks ASIC Design Engineers to contribute to architecture, microarchitecture, and RTL for high‑performance SoC interconnects and memory controllers.

You will work with architecture, verification, and physical design teams to deliver power‑efficient silicon across product cycles and collaborate on C/C++ modeling and RTL workflows. The role emphasizes design quality, timing closure, and cross‑functional collaboration in a fast-paced hardware environment