Staff Serdes Analog Design Engineer — High-Speed IP

Samsung-Semiconductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

Paid time off

Fertility support

Medical travel support

Onsite gym

Job summary

Samsung Semiconductor, headquartered in San Jose, CA, is seeking an expert for high-speed Serdes architecture and analog/mixed-signal circuit design. You will contribute to Serdes IPs, clocking, and interconnects, working with cutting‑edge processes to deliver high-performance, low-power solutions.

The role requires extensive experience in CMOS analog/digital design, EDA tools, and scripting, with a strong collaboration mindset and willingness to adapt to evolving tech stacks.

Qualifications

• Bachelor's degree with 10+ years, Master's with 8+ years or PhD with 5+ years of experience.
• Knowledge and experience with analog circuits/mixed signal circuits: bandgap, LDO, filters.
• Knowledge and experience with Serdes IPs: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
• Knowledge of Serdes architecture and high-speed interconnect standards (USB, PCIe, UCIe).
• Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.
• Well‑versed in EDA tools (Cadence, Spectre, Totem, EMX).
• Comfortable with scripting languages (Python, Matlab).
• You’re inclusive and collaborative, with a learner mindset.

Responsibilities

• Design low‑power and low‑voltage analog and custom digital circuit components using advanced CMOS process technologies.
• Translate component design specifications to schematics and build test benches to evaluate performance, power, and reliability.
• Supervise layout designers to generate LVS/DRC clean layouts and optimize for power and performance.
• Validate functionality and performance in silicon.

Skills

Analog circuits

Mixed signal

Serdes IPs

EDA tools

Python scripting

Team collaboration

Education

Bachelor's degree

Master's degree

PhD

Tools

Cadence

Spectre

Totem

EMX

Job description

Samsung Semiconductor, headquartered in San Jose, CA, is seeking an expert for high-speed Serdes architecture and analog/mixed-signal circuit design. You will contribute to Serdes IPs, clocking, and interconnects, working with cutting‑edge processes to deliver high-performance, low-power solutions.

The role requires extensive experience in CMOS analog/digital design, EDA tools, and scripting, with a strong collaboration mindset and willingness to adapt to evolving tech stacks.