Senior High-Speed PHY & IO Design Engineer

Sandisk; Milpitas (CA); Vor Ort; USD 140.000 - 210.000; Vollzeit

Zusammenfassung

Sandisk in Milpitas, CA is seeking an experienced VLSI Design Engineer to contribute to high-speed PHY development and timing analysis.

You will work across disciplines, document results, and present findings to global teams. Requires 5+ years in high-speed interfaces like NAND toggling modes and LPDDR/GDDR.

The role is exempt, with competitive compensation and a broad benefits package.

Qualifikationen

• BS/MS in Electronics & Electrical Engineering with 5+ years in NAND/FLASH protocols and high-speed interfaces such as DDR/LPDDR/GDDR.
• Deep understanding of High-Speed PHY and Datapath architectures and clock recovery schemes.
• Experience with Cadence/Synopsys toolchains and statistical simulation methodologies.
• Experience in mixed-mode simulation and analog/digital co-simulation is a plus.
• Experience creating EDA models such as Verilog models or Liberty is a plus.

Aufgaben

• Thorough understanding of High-Speed PHY and clock recovery.
• Timing budgeting and analysis in custom high-speed designs.
• SI/PI Analysis with models like IBIS/SPF.
• Analytical and able to work in a multi-disciplinary environment.
• Good documentation and presentation skills.

Kenntnisse

High-Speed PHY

Timing budgeting

SI/PI Analysis

Clock recovery

Verilog model

Cross-functional collaboration

Ausbildung

Bachelors/Masters in Electronics & Electrical Engineering

Tools

Cadence Virtuoso

Synopsys tools

HSPice

Spectre

Finesim

Jobbeschreibung

Sandisk in Milpitas, CA is seeking an experienced VLSI Design Engineer to contribute to high-speed PHY development and timing analysis.

You will work across disciplines, document results, and present findings to global teams. Requires 5+ years in high-speed interfaces like NAND toggling modes and LPDDR/GDDR.

The role is exempt, with competitive compensation and a broad benefits package.