Senior HBM & High-Speed Interface Architect

Micron Technology; Richardson (TX); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology seeks a senior memory interface architect to own HBM IO blocks and subsystems from architectural definition through silicon bring-up and post-silicon debug. You will define PHY interfaces, clocking, training, calibration, and power-management requirements for advanced heterogeneous systems.

Lead cross‑functional teams across front-end, layout, SI/PI, thermal, and packaging to optimize 2.5D/3D memory-interface implementations and drive robust, high‑performance builds for AI/HPC

Qualifications

• 18+ years in memory/High-speed interface design (HBM, DDR, LPDDR).
• Proven track record delivering IP/subsystems from architecture to silicon bring-up.
• Expertise in high-speed memory interface architecture and analog/mixed-signal design.

Responsibilities

• Own and deliver HBM IO blocks and subsystems from spec to silicon bring-up.
• Define HBM PHY, die-to-die interfaces, clocking, training, calibration, and power management.
• Lead pre/post-silicon issue analysis and multidisciplinary coordination across teams.
• Mentor engineers through architecture/build reviews and problem solving.

Skills

HBM/DDR high-speed interfaces

RTL design & verification

Analog/mixed-signal design

Front-end implementation & timing

SystemVerilog

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Tools

Verilog/SystemVerilog

HSPICE/FastSPICE

RTL verification tools

Job description

Micron Technology seeks a senior memory interface architect to own HBM IO blocks and subsystems from architectural definition through silicon bring-up and post-silicon debug. You will define PHY interfaces, clocking, training, calibration, and power-management requirements for advanced heterogeneous systems.

Lead cross‑functional teams across front-end, layout, SI/PI, thermal, and packaging to optimize 2.5D/3D memory-interface implementations and drive robust, high‑performance builds for AI/HPC