HBM Interface Architect, Lead Memory Subsystems

Micron Technology, Inc.; Richardson (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Micron Technology, Inc. in Richardson, TX, seeks an experienced Interface Design Architect to lead high-speed memory subsystem interfaces.

You will own HBM PHY, controller-to-PHY, die-to-die interfaces and drive pre-silicon to post-silicon activities across multiple teams. The role demands deep knowledge of DRAM operation, JEDEC specs, analog/mixed-signal design, RTL, timing, and power management, plus strong cross-functional leadership to deliver scalable memory solutions for AI and HPC

Qualifications

• 18+ years of experience in high-speed memory or related IC design roles.
• Experience delivering interface IP from architecture to silicon bring-up and post-silicon debug.
• Strong expertise in high-speed memory-interface architecture and HBM familiarity.

Responsibilities

• Own and deliver HBM IO blocks and subsystems from architecture through silicon bring-up.
• Define HBM PHY, controller-to-PHY, die-to-die interfaces including training and calibration.
• Lead architecture and design of analog, mixed-signal, and digital interface functions for high-speed memory subsystems.
• Collaborate with package, interposer, physical design, signal integrity, and thermal teams to optimize interfaces across 2.5D/3D systems.
• Mentor engineers and drive execution across architecture, design, verification, validation, packaging, and product engineering teams.

Skills

HBM PHY design

RTL design

Analog/mixed-signal design

Clocking and training

Power management

Pre-silicon to post-silicon

Cross-functional leadership

JEDEC specifications

Memory subsystem architecture

Debug and validation

Education

Bachelor’s degree in Electrical/Computer Engineering

Tools

Verilog

SystemVerilog

FastSpice/HSPice

RTL verification tools

Job description

Micron Technology, Inc. in Richardson, TX, seeks an experienced Interface Design Architect to lead high-speed memory subsystem interfaces.

You will own HBM PHY, controller-to-PHY, die-to-die interfaces and drive pre-silicon to post-silicon activities across multiple teams. The role demands deep knowledge of DRAM operation, JEDEC specs, analog/mixed-signal design, RTL, timing, and power management, plus strong cross-functional leadership to deliver scalable memory solutions for AI and HPC