HBM Interface Architect: Lead High-Speed Memory Design

Micron; Richardson (TX); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision plan

Paid time off

Job summary

Micron Technology is seeking a senior memory interface engineer to own HBM IO blocks from architecture through silicon bring-up and post-silicon debugging. You will define HBM PHYs, die-to-die interfaces, and training/calibration strategies for high-speed memory subsystems.

You will lead architecture and design of analog, mixed-signal, and digital interfaces and work with packaging, SI/PI, and thermal teams to optimize performance. A strong background in RTL/verification is required.

Qualifications

• 18+ years of experience in memory/interfaces or related IC design roles.
• Experience delivering complex interface IP from architecture to post-silicon debug.
• Strong expertise in high-speed memory-interface architecture and design.

Responsibilities

• Own and deliver critical HBM IO blocks and subsystems from architectural definition through silicon bring-up and post-silicon debug.
• Define HBM PHY, controller-to-PHY, die-to-die interfaces, clocking, training, calibration, power-management, and test requirements.
• Lead architecture and design of analog, mixed-signal, and digital interface functions for high-speed memory subsystems.
• Mentor engineers through architecture and build reviews and improve IP reuse and execution rigor.

Skills

HBM Architecture

High-speed memory

RTL design

Analog & mixed-signal

Technical leadership

Front-end verification

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Verilog

SystemVerilog

HSPICE

FastSPICE

Job description

Micron Technology is seeking a senior memory interface engineer to own HBM IO blocks from architecture through silicon bring-up and post-silicon debugging. You will define HBM PHYs, die-to-die interfaces, and training/calibration strategies for high-speed memory subsystems.

You will lead architecture and design of analog, mixed-signal, and digital interfaces and work with packaging, SI/PI, and thermal teams to optimize performance. A strong background in RTL/verification is required.