HBM Architecture Lead for AI & HPC

Micron Technology, Inc; Richardson (TX); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. seeks an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products.

You will shape PHY IO architecture, timing methodology, and calibration schemes, collaborating across design, modeling, packaging, and system teams to translate concepts into silicon. The role emphasizes architectural leadership, device learning, and mentoring, influencing roadmap directions and engineering methodologies

Qualifications

• MS or PhD in Electrical Engineering or a related field.
• 7+ years of experience in semiconductor design, architecture, or technology development.
• Expertise in analog and mixed-signal IO design and architecture.
• Deep knowledge of high-speed transmitter, receiver, clocking, and timing architectures.

Responsibilities

• Define and drive next-generation HBM PHY and IO architecture.
• Architect high-performance transmit and receive paths, including clocking, signaling, equalization, timing alignment, and interface optimization.
• Define and optimize analog calibration architectures and timing calibration schemes.
• Develop IO timing budgets, design targets and margin methodologies across PVT variations.

Skills

Analog & mixed-signal IO design

High-speed TX/RX architectures

Clocking & timing

IO timing budgets & margin

Technical communication

Education

MS or PhD in Electrical Engineering

Job description

Micron Technology, Inc. seeks an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products.

You will shape PHY IO architecture, timing methodology, and calibration schemes, collaborating across design, modeling, packaging, and system teams to translate concepts into silicon. The role emphasizes architectural leadership, device learning, and mentoring, influencing roadmap directions and engineering methodologies