HBM IO Architect | Principal Engineer - High-Speed Memory

Micron Technology, Inc.; Texas; Sur place; USD 140 000 - 190 000; Plein temps

Avantages offerts par ce poste

Medical, dental, and vision plans

Paid time-off and holidays

Retirement benefits

Résumé du poste

Micron Technology, Inc. in the United States (Texas) is seeking a Principal Engineer to lead HBM IO design architecture, shaping multi-generation IP and silicon-validation strategies.

You will drive TSV-based link architectures, IO training features, and high-speed IO circuit design to achieve top-tier bandwidth and power efficiency. The role requires leadership in cross-functional teams and deep expertise in analog/mixed-signal CMOS, with a track record of silicon success in memory or

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent experience.
• 7+ years in memory or high-speed IO design with proven silicon success.
• Deep expertise in analog and mixed-signal CMOS circuit design and simulation.
• Strong experience with high-speed IO architectures such as Rx/Tx, PLL, DLL, DCC, phase interpolators, or equalizers.

Responsabilités

• Define and own HBM IO and data path architecture across multiple product generations from pathfinding through tape-out.
• Architect and analyze TSV-based HBM link schemes including topology, signaling strategy, and parasitic co-design.
• Define and drive HBM PHY IO training features to ensure robust PVT margin across product generations.
• Architect high-speed IO circuits for the HBM interface die targeting best-in-class bandwidth and power efficiency.
• Establish IO and TSV design standards and drive alignment across design, product, package, and process teams.

Connaissances

High-speed IO design

CMOS analog/mixed-signal

IO architectures

Formation

Bachelor's degree in Electrical Engineering or equivalent experience

Master's degree or PhD in Electrical Engineering or related field

Description du poste

Micron Technology, Inc. in the United States (Texas) is seeking a Principal Engineer to lead HBM IO design architecture, shaping multi-generation IP and silicon-validation strategies.

You will drive TSV-based link architectures, IO training features, and high-speed IO circuit design to achieve top-tier bandwidth and power efficiency. The role requires leadership in cross-functional teams and deep expertise in analog/mixed-signal CMOS, with a track record of silicon success in memory or