HBM Interface Architect for High-Performance Memory

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Retirement plan

Job summary

Micron Technology, Inc. is seeking a senior engineer to own and deliver critical HBM IO blocks and subsystems from architectural definition through silicon bring-up.

You will define HBM PHYs, die-to-die interfaces, training and power-management, coordinating with architecture, design, and package teams across 2.5D/3D systems. The role requires deep knowledge of DRAM operation, HBM/DDR interfaces, and JEDEC specs, with leadership across multidisciplinary teams to drive pre/post-silicon debugging

Qualifications

• Experience in HBM/DDR/LPDDR interfaces and high-speed memory subsystems.
• Experience delivering interface IP or subsystems from architecture to silicon bring-up.
• Strong knowledge of JEDEC specifications and mixed-signal design.

Responsibilities

• Own and deliver HBM IO blocks and subsystems from architecture to tape-out and post-silicon debug.
• Define HBM PHY, controller-to-PHY, die-to-die interfaces and test requirements.
• Lead problem solving across circuit design, RTL, and system interactions.
• Coordinate across architecture, design, layout, packaging, test, and product engineering teams.
• Research and influence next-generation HBM, CPO, chiplet architectures for AI/HPC workloads.

Skills

HBM memory architectures

mixed-signal design

RTL design

front-end implementation

project leadership

communication skills

Verilog/SystemVerilog

high-speed interfaces

Education

Bachelors in Electrical/Computer Engineering

Tools

Verilog

SystemVerilog

Job description

Micron Technology, Inc. is seeking a senior engineer to own and deliver critical HBM IO blocks and subsystems from architectural definition through silicon bring-up.

You will define HBM PHYs, die-to-die interfaces, training and power-management, coordinating with architecture, design, and package teams across 2.5D/3D systems. The role requires deep knowledge of DRAM operation, HBM/DDR interfaces, and JEDEC specs, with leadership across multidisciplinary teams to drive pre/post-silicon debugging