HBM IO Design Architect for AI/ML Memory

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off and holidays

Competitive benefits

Job summary

Micron Technology, Inc. in Richardson, TX, is seeking an HBM IO Design Architecture Engineer to own the end-to-end design quality system for high‑bandwidth memory projects.

You will drive design quality processes, silicon data analysis, and cross‑team data collection to ensure learnings feed back into the next generation design. The ideal candidate has 10+ years in high‑speed IO/clocking design (32Gbps+), strong analog/digital skills, verification, parasitic extractions, and familiarity with

Qualifications

• 10+ years of relevant engineering or design experience in high-speed IO, PLL, Tx/Rx, and clocking
• Strong background in analog and digital IO design and simulation
• Experience with circuit verification and layout parasitic extraction
• Familiar with off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc
• Excellent documentation and communication skills

Responsibilities

• High-speed IO design architecture for HBM products
• Define and standardize IO design quality process from architecture to silicon
• Correlate silicon measurements and simulation performance for circuit level design analysis
• Contribute to cross group communication to standardize and enable group success
• Solicit input from Standards, CAD, modeling, and verification groups for design quality
• Drive innovation into future memory generation with AI-assisted analytics

Skills

High-speed IO design

Analog and digital design

Design verification

Parasitic extraction

Communication & documentation

Cross-functional collaboration

Education

MS or PhD in EE

Job description

Micron Technology, Inc. in Richardson, TX, is seeking an HBM IO Design Architecture Engineer to own the end-to-end design quality system for high‑bandwidth memory projects.

You will drive design quality processes, silicon data analysis, and cross‑team data collection to ensure learnings feed back into the next generation design. The ideal candidate has 10+ years in high‑speed IO/clocking design (32Gbps+), strong analog/digital skills, verification, parasitic extractions, and familiarity with