Senior GPU Front-End Implementation Engineer

MaziCTools; United States; Remote; USD 180,000 - 230,000; Full time

Job summary

Apple in Austin, TX is seeking a Graphics FE Implementation Engineer to drive RTL to GDS design, and optimize timing, power, and area for Apple Silicon GPUs. You will collaborate with RTL, PD, STA, and DFT teams to deliver high-performance IP for world-class products.

The role emphasizes advanced synthesis, timing analysis, floorplanning, memory optimization, and ECOs, with scripting in Python/Tcl/Perl to automate flows. A BS with extensive experience is required.

Qualifications

• BS + minimum of 15 years of experience in ASIC/SoC design.
• Experience with RTL design principles and physical design implementation to optimize area, timing, and power.
• Experience with floor-planning, placement, timing constraints, and congestion.
• Experience debugging complex logic and driving ECOs for functionality and timing.
• Proficiency in scripting across Python, Tcl, and Perl for ASIC flows.

Responsibilities

• Synthesize, analyze, and optimize delivered IP for timing, power, and area targets.
• Collaborate with STA and DFT teams to achieve successful first silicon.
• Lead partition level implementation and drive multi-block closure across RTL and Physical Design.
• Debug and review netlists to ensure functionality and quality of netlists.
• Develop and adopt innovative methodologies for design optimization and automation.

Skills

RTL design principles

Advanced synthesis techniques

RTL optimization

Physical design basics

Floor-planning

Timing analysis

Memory optimization

Python scripting

Tcl scripting

Perl scripting

Data manipulation

Education

Bachelor's degree (BS) or equivalent

Tools

Structured placement

Memory optimization

Reset domain

Multi-clock domain

UPF (Power domain)

RTL linting tools

Python scripting

Tcl scripting

Perl scripting

Data manipulation

Job description

Apple in Austin, TX is seeking a Graphics FE Implementation Engineer to drive RTL to GDS design, and optimize timing, power, and area for Apple Silicon GPUs. You will collaborate with RTL, PD, STA, and DFT teams to deliver high-performance IP for world-class products.

The role emphasizes advanced synthesis, timing analysis, floorplanning, memory optimization, and ECOs, with scripting in Python/Tcl/Perl to automate flows. A BS with extensive experience is required.