GPU RTL Design Engineer for High-Performance SoC

Apple Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Austin, TX is seeking an experienced RTL design engineer to help design and verify high-performance SoCs for mobile GPUs. You will collaborate with Platform Architecture, Software, Design Verification and Physical Design teams to deliver RTL and specifications for GPU power management and SOC interface logic.

Join a group focused on delivering power-efficient, reliable silicon. You’ll drive timing, area, and power goals, integrate IP from other teams, and ensure rigorous design

Qualifications

• BS in EE, CE or ECE required.
• Experience in logic optimization, synthesis, timing analysis, floor-planning, power intent descriptions, and clock domain crossings.
• Experience writing RTL in Verilog and/or System Verilog; experience with logic simulation and debug.

Responsibilities

• Deliver high quality design collateral, including RTL, to Physical Design teams.
• Assess and integrate IP from other Apple teams.
• Close timing, power, area, and lint for design by optimizing RTL and constraints.
• Drive performance, power, area, and functional goals.
• Provide schedules to IP teams and management.
• Collaborate effectively with IP teams spanning multiple sites.

Skills

Logic optimization

Synthesis

Timing analysis

Floor planning

Clock domain crossing

Power intent descriptions

Debugging

Education

BS in EE, CE or ECE

Tools

Verilog/SystemVerilog RTL

Logic simulation

Job description

Apple Inc. in Austin, TX is seeking an experienced RTL design engineer to help design and verify high-performance SoCs for mobile GPUs. You will collaborate with Platform Architecture, Software, Design Verification and Physical Design teams to deliver RTL and specifications for GPU power management and SOC interface logic.

Join a group focused on delivering power-efficient, reliable silicon. You’ll drive timing, area, and power goals, integrate IP from other teams, and ensure rigorous design