GPU Frontend RTL & Netlist Engineer

Apple Inc.; United States; On-site; USD 140,000 - 210,000; Full time

Job summary

Apple Inc. is seeking an experienced engineer for RTL to netlist generation on Apple Silicon GPUs. You’ll collaborate with RTL and Physical design teams to deliver high‑quality netlists and meet critical milestones.

In this role, you’ll perform linting, CDC and logic‑equivalence checks and support ECO generation activities to drive best‑in‑class GPU performance. The position emphasizes collaboration, strong fundamentals in digital logic, and hands-on use of Verilog/SystemVerilog and RTL tools in

Qualifications

• BS in Electrical Engineering or related field.
• Coursework in Computer Architecture, Digital Logic Design and CMOS VLSI design.
• Experience with scripting languages (Python/Perl/Tcl).

Responsibilities

• RTL to netlist generation in collaboration with the RTL and Physical design teams.
• Deliver key netlist quality milestones for your partition.
• Engage in Lint, CDC, Logic equivalence checks and support ECO generation activities.
• Contribute to delivering best-in-class GPUs for Apple Silicon.

Skills

Digital logic design

Scripting (Python/Perl/Tcl)

Computer architecture

Education

BS in Electrical Engineering or related field

Tools

rtl2gds tools

Synthesis

Place & Route

Static timing analysis

DFT methodologies

Verilog/SystemVerilog

Job description

Apple Inc. is seeking an experienced engineer for RTL to netlist generation on Apple Silicon GPUs. You’ll collaborate with RTL and Physical design teams to deliver high‑quality netlists and meet critical milestones.

In this role, you’ll perform linting, CDC and logic‑equivalence checks and support ECO generation activities to drive best‑in‑class GPU performance. The position emphasizes collaboration, strong fundamentals in digital logic, and hands-on use of Verilog/SystemVerilog and RTL tools in