GPU RTL Design Engineer - SystemVerilog

Apple Inc.; Austin, Northern (TX, KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Apple Inc. in Austin, TX is seeking a qualified engineer to write SystemVerilog RTL for GPU microarchitecture, perform synthesis, timing analysis, and collaborate with verification and backend teams to optimize PPA. The role requires a Master’s in ECE or related field, strong SystemVerilog, CAD tools, and GPU design experience, plus Perl/Python scripting.

40 hours/week, onsite. You will participate in design reviews, test plan reviews, and ensure full coverage while coordinating with

Qualifications

• Master’s degree in Electrical and Computer Engineering or related field.
• Experience in Computer Architecture and Microarchitecture for GPU blocks.
• Experience with RTL coding using SystemVerilog.
• Experience with synthesis and timing analysis for area and power optimization.
• Utilizing CAD tools for debug and synthesis.
• Experience with VLSI design to design GPUs.
• Experience with scripting languages such as Perl/Python.
• Experience with GPUs.

Responsibilities

• Write SystemVerilog RTL code based on GPU microarchitecture specs.
• Simulate and debug RTL using CAD tools to ensure design correctness.
• Synthesize the design and analyze area, power, and timing reports to verify PPA goals.
• Collaborate with verification engineers to review test plans, debug failures, and ensure full coverage.
• Collaborate with backend and synthesis teams to review placement and routing feedback and make design adjustments accordingly.
• Participate in design and architecture reviews to discuss interface definitions, data flows, and module responsibilities.
• Perform timing analysis and optimize design logic to meet critical path constraints.
• Coordinate with cross-functional team members to align schedules, resolve issues, and support the integration of my module into the full chip.

Skills

SystemVerilog

GPU Architecture

Scripting (Perl/Python)

RTL Coding

Timing Analysis

Education

Master's degree in Electrical and Computer Engineering

Tools

CAD Tools

Synthesis Tools

SystemVerilog

Job description

Apple Inc. in Austin, TX is seeking a qualified engineer to write SystemVerilog RTL for GPU microarchitecture, perform synthesis, timing analysis, and collaborate with verification and backend teams to optimize PPA. The role requires a Master’s in ECE or related field, strong SystemVerilog, CAD tools, and GPU design experience, plus Perl/Python scripting.

40 hours/week, onsite. You will participate in design reviews, test plan reviews, and ensure full coverage while coordinating with