Senior Frontend Design Lead — RTL, IP & SoC Innovation

Cadence; Austin (TX); Vor Ort; USD 170.000 - 210.000; Vollzeit

Zusammenfassung

Cadence Solutions (North America) seeks an experienced Front End Design leader to guide RTL design projects in the semiconductor space. You will mentor a team of RTL engineers and drive features that meet performance, power, and area goals.

You will work with DV, PD, architecture and firmware to ensure timely delivery, with hands-on RTL development in Verilog/SystemVerilog/VHDL and oversight of verification activities.

Qualifikationen

• BS/MS in engineering or computer science required.
• 10+ years in front end design or verification with leadership experience.
• Proven track record in IP/SoC integration and multi-disciplinary projects.

Aufgaben

• Lead and mentor RTL design engineers to deliver projects on schedule.
• Define microarchitectural features for IPs and subsystems to meet PPA goals.
• Write, debug, and optimize RTL in Verilog, SystemVerilog, or VHDL.
• Oversee pre-silicon verification (Lint, CDC, FV) and coordinate with DV/PD/architecture/firmware teams.

Kenntnisse

Front End Leadership

RTL design & verification

Verilog/SystemVerilog/VHDL

Team leadership

Cross-functional collaboration

Ausbildung

BS/MS Engineering or Computer Science

Tools

Cadence Front End Toolset

Jobbeschreibung

Cadence Solutions (North America) seeks an experienced Front End Design leader to guide RTL design projects in the semiconductor space. You will mentor a team of RTL engineers and drive features that meet performance, power, and area goals.

You will work with DV, PD, architecture and firmware to ensure timely delivery, with hands-on RTL development in Verilog/SystemVerilog/VHDL and oversight of verification activities.