Group Director, Design Engineering - Front End

Cadence; Austin (TX); On-site; USD 170,000 - 210,000; Full time

Job summary

Cadence Solutions (North America) seeks an experienced Front End Design leader to guide RTL design projects in the semiconductor space. You will mentor a team of RTL engineers and drive features that meet performance, power, and area goals.

You will work with DV, PD, architecture and firmware to ensure timely delivery, with hands-on RTL development in Verilog/SystemVerilog/VHDL and oversight of verification activities.

Qualifications

• BS/MS in engineering or computer science required.
• 10+ years in front end design or verification with leadership experience.
• Proven track record in IP/SoC integration and multi-disciplinary projects.

Responsibilities

• Lead and mentor RTL design engineers to deliver projects on schedule.
• Define microarchitectural features for IPs and subsystems to meet PPA goals.
• Write, debug, and optimize RTL in Verilog, SystemVerilog, or VHDL.
• Oversee pre-silicon verification (Lint, CDC, FV) and coordinate with DV/PD/architecture/firmware teams.

Skills

Front End Leadership

RTL design & verification

Verilog/SystemVerilog/VHDL

Team leadership

Cross-functional collaboration

Education

BS/MS Engineering or Computer Science

Tools

Cadence Front End Toolset

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.

This is a leadership role where you will be responsible for:

Technical Leadership:

Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.

Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.

RTL Development:

Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.

Verification & Signoff:

Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.

Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Qualifications:

• 10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
• Proven experience in leading and managing complex engineering projects
• Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
• Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
• Experience in driving results in multi-disciplinary organization

A Self-motivated person with good communication and design management skills

Experience with Cadence front end toolset

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