Front End Design Engineering Director

Cadence Design Systems; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

Cadence is seeking an experienced Front End Design lead in the Austin area to guide RTL engineers and drive IP/SOC integration. You will oversee pre-silicon verification and collaborate with DV, PD, and firmware teams to ensure on-time delivery.

The role emphasizes technical leadership, microarchitectural feature development, and hands-on RTL/synthesis activities to meet aggressive PPA goals. Cadence offers an inclusive, innovation-driven environment.

Qualifications

• 10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences.
• Proven experience in leading and managing complex engineering projects.
• Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration.
• Expert in RTL design (Verilog), simulators debuggers.
• Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
• Experience in driving results in multi-disciplinary organization.

Responsibilities

• Lead Front End design projects, guide and mentor RTL design engineers.
• Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
• RTL development: write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL.
• Verification & Signoff: oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
• Collaboration: work closely with cross-functional teams, including DV, PD, Architecture, and firmware engineers, to ensure successful delivery.

Skills

Front End design leadership

IP creation & SoC integration

RTL design (Verilog)

Synthesis & SDC

Cross-functional leadership

Multi-disciplinary collaboration

Education

BS/MS in Engineering or Computer Sciences

Tools

Cadence front end tools

Job description

Cadence is seeking an experienced Front End Design lead in the Austin area to guide RTL engineers and drive IP/SOC integration. You will oversee pre-silicon verification and collaborate with DV, PD, and firmware teams to ensure on-time delivery.

The role emphasizes technical leadership, microarchitectural feature development, and hands-on RTL/synthesis activities to meet aggressive PPA goals. Cadence offers an inclusive, innovation-driven environment.