RTL Design Manager for Front-End SoC Innovation

AMD; San Jose (CA); On-site; USD 150,000 - 180,000; Full time

Job summary

AMD is seeking an RTL Design Manager for the AECG IP & SOC group in San Jose, CA. You will lead a small team, own RTL block design, and guide verification while driving automation to improve efficiency. Strong front-end RTL background and clear communication with executives are essential.

The role collaborates with architecture, IP design, and Physical Design teams to ensure first-pass silicon success and scalable design practices.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• Experience leading an engineering team and designing RTL blocks.
• Strong front-end RTL engineering background and ability to summarize complex problems for executives.

Responsibilities

• Lead a small, high-performance engineering team.
• Own the design and implementation of blocks to meet functional, timing, area and power requirements.
• Guide and review verification for these blocks.
• Design and implement logic functions that enable efficient test and debug.
• Implement automation to increase design team efficiency.
• Strong communication skills to summarize complex problems for executives.

Skills

RTL design

Communication skills

Problem solving

Automation scripting

Education

Bachelor's or Master's in Electrical Engineering / Computer Engineering

Tools

Python

Perl

Tcl

APB/AXI protocols

Job description

AMD is seeking an RTL Design Manager for the AECG IP & SOC group in San Jose, CA. You will lead a small team, own RTL block design, and guide verification while driving automation to improve efficiency. Strong front-end RTL background and clear communication with executives are essential.

The role collaborates with architecture, IP design, and Physical Design teams to ensure first-pass silicon success and scalable design practices.