Senior FPGA Prototyping Architect

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys seeks a seasoned FPGA/ASIC verification and prototyping expert to lead deployments of HAPS-200 and ProtoCompiler for strategic customers across AI/ML, automotive, and hyperscaler segments.

You will own partitioning, timing closure, and bring-up on multi-FPGA systems, mentor engineers worldwide, and collaborate with R&D, product management, and sales to shape the roadmap and customer success.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years in FPGA implementation, ASIC design/verification, or hardware-assisted verification.
• Deep expertise with FPGA synthesis, place-and-route, multi-FPGA partitioning and timing closure.
• Proficiency in SystemVerilog, UVM, assertions, and verification testbenches.
• Hands-on experience with PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or SerDes protocols.
• Proficiency in Tcl, Python, or shell scripting for automation and flow development.
• Direct experience with Synopsys HAPS and ProtoCompiler; familiarity with ZeBu/Palladium/Protium/Veloce is a plus.

Responsibilities

• Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs.
• Drive the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, P&R, timing, and bring-up on multi-FPGA systems.
• Debug complex interface IP subsystems including DDR4/DDR5, PCIe, Ethernet, and SerDes architectures.
• Reproduce, analyze, and resolve critical customer escalations related to RTL, timing, and bring-up issues.
• Collaborate with ProtoCompiler R&D and Product Management to validate features and capture customer requirements.
• Develop reusable methodologies for partitioning, clock architecture, and hardware/software co-validation.
• Mentor applications engineers globally and represent Synopsys at customer sites and industry events.

Skills

FPGA synthesis

Place-and-route

Multi-FPGA partitioning

Timing closure

Constraint development

SystemVerilog

UVM

Verdi/trace tooling

Scripting (Tcl/Python)

Emulation/prototyping concepts

Education

Bachelor's, Master's, or PhD in Electrical/Computer Engineering or Computer Science

Tools

Xilinx Vivado

Intel Quartus

Synopsys HAPS

ProtoCompiler

ZeBu / Palladium / Protium / Veloce

Job description

Synopsys seeks a seasoned FPGA/ASIC verification and prototyping expert to lead deployments of HAPS-200 and ProtoCompiler for strategic customers across AI/ML, automotive, and hyperscaler segments.

You will own partitioning, timing closure, and bring-up on multi-FPGA systems, mentor engineers worldwide, and collaborate with R&D, product management, and sales to shape the roadmap and customer success.