Lead FPGA Prototyping Engineer for Billion-Gate SoCs

Synopsys; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys is seeking a senior Hardware‑Assisted Verification expert to lead deployments of HAPS-200 and ProtoCompiler for strategic customers building billion‑gate SoCs across AI, automotive, hyperscaler, and aerospace segments.

You will drive the full ASIC‑to‑FPGA flow, debug complex interfaces, mentor engineers globally, and influence roadmaps by translating customer needs into practical verification solutions in production environments.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands‑on experience.
• 10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation.
• Deep expertise in FPGA synthesis, place-and-route, multi‑FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools.
• Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture.
• Hands‑on experience with interface IP including PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or high‑speed SerDes protocols.
• Proficiency in Tcl, Python, or shell scripting for automation and flow development.
• Direct experience with Synopsys HAPS and ProtoCompiler is a strong plus, as is experience with ZeBu, Palladium, Protium, or Veloce emulation platforms.

Responsibilities

• Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs across AI/ML, automotive, hyperscaler, and aerospace segments.
• Drive the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, bitstream generation, and hardware bring-up on multi-FPGA systems.
• Debug complex interface IP subsystems including DDR4/DDR5, LPDDR5/6/7, HBM, PCIe Gen3-6, CXL, UCIe, Ethernet, USB, AXI, and high-speed SerDes architectures.
• Reproduce, analyze, and resolve critical customer escalations involving RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures.
• Collaborate directly with ProtoCompiler R&D and Product Management to validate new features, influence roadmap priorities, and represent customer requirements in product planning.
• Develop and document reusable methodologies for partitioning strategies, clock architecture, debug instrumentation, verification environment adaptation, and hardware/software co-validation.
• Mentor applications engineers globally, lead technical workshops and architecture reviews, and represent Synopsys at customer sites, conferences, and industry forums.

Skills

FPGA implementation

ASIC design

ASIC verification

FPGA prototyping

emulation

SystemVerilog

UVM

assertions

functional coverage

verification testbench

Tcl scripting

Python scripting

shell scripting

debug instrumentation

ProtoCompiler

HAPS-200

multi-FPGA flow

Education

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science

Tools

Xilinx Vivado

Intel Quartus

Synopsys HAPS

ProtoCompiler

ZeBu

Palladium

Protium

Veloce

Job description

Synopsys is seeking a senior Hardware‑Assisted Verification expert to lead deployments of HAPS-200 and ProtoCompiler for strategic customers building billion‑gate SoCs across AI, automotive, hyperscaler, and aerospace segments.

You will drive the full ASIC‑to‑FPGA flow, debug complex interfaces, mentor engineers globally, and influence roadmaps by translating customer needs into practical verification solutions in production environments.