FPGA & ASIC Prototyping Applications Engineer

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Synopsys, Inc. is seeking a skilled engineer to support customer deployments of HAPS and ProtoCompiler for FPGA-based prototyping. You will work with R&D to diagnose RTL, timing, and hardware issues and help customers bring up prototypes on schedule.

You will engage with interface IP such as PCIe, DDR, Ethernet, and AXI, and collaborate with Sales and Customer Success for evaluations and PoCs. A strong background in FPGA flows and scripting is required.

Qualifications

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 5–8 years in FPGA implementation, ASIC design, ASIC verification, FPGA prototyping, or applications engineering.
• Strong experience with FPGA synthesis, place-and-route, and timing closure using Xilinx Vivado, Intel Quartus, or similar tools.
• Working knowledge of SystemVerilog, RTL design, and verification concepts.
• Hands-on experience with interface IP families such as PCIe, DDR, Ethernet, USB, or AXI.
• Scripting ability in Tcl, Python, or shell for automation and flow customization.
• Experience with Synopsys HAPS, ProtoCompiler, or other FPGA-based prototyping platforms is a strong plus.

Responsibilities

• Support customer deployments of HAPS and ProtoCompiler across the ASIC-to-FPGA flow, including partitioning, synthesis, place-and-route, timing closure, and hardware bring-up.
• Debug customer designs involving interface IP such as DDR4/DDR5, PCIe, Ethernet, USB, AXI, and more.
• Reproduce and analyze technical issues reported by customers, collaborating with R&D to identify root causes and deliver solutions or workarounds.
• Develop and document methodologies for partitioning strategies, clock architecture, debug instrumentation, and bring-up procedures.
• Collaborate with Sales and Customer Success teams to support evaluations, PoCs, and deployment planning.
• Use Verdi, ProtoCompiler runtime debug tools, and protocol analyzers to troubleshoot RTL, netlist, timing, and hardware issues.

Skills

SystemVerilog

RTL design

Verification concepts

Scripting

Customer communication

Education

B.E./B.S. in Electrical/Computer Engineering or CS

Tools

Xilinx Vivado

Intel Quartus

Verdi

ProtoCompiler

Job description

Synopsys, Inc. is seeking a skilled engineer to support customer deployments of HAPS and ProtoCompiler for FPGA-based prototyping. You will work with R&D to diagnose RTL, timing, and hardware issues and help customers bring up prototypes on schedule.

You will engage with interface IP such as PCIe, DDR, Ethernet, and AXI, and collaborate with Sales and Customer Success for evaluations and PoCs. A strong background in FPGA flows and scripting is required.