Senior FPGA Prototyping Engineer (HAPS & Multi-FPGA)

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Synopsys, Inc. is seeking a senior FPGA/RTL design engineer to enable HAPS prototyping platforms. You will lead FPGA development, from RTL changes to timing closure and hardware validation on AMD/Xilinx devices, collaborating across hardware, software, and manufacturing teams.

You will build automation tools in Python/C++, validate high-speed interfaces, perform PRBS testing, and analyze eye diagrams, jitter, and link margins to ensure production-ready results.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of hands-on FPGA and RTL design experience.
• Expert-level proficiency in SystemVerilog/Verilog for RTL design, with clocking architectures and timing analysis.
• Extensive experience with AMD/Xilinx FPGA synthesis, place-and-route, and timing closure using Vivado.

Responsibilities

• Develop FPGA-optimized implementations for HAPS platforms, addressing capacity limits, timing constraints, and multi-FPGA partitioning challenges.
• Own the full FPGA development cycle from RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices.
• Drive board and system bring-up for HAPS prototyping hardware, including functional validation, performance characterization, signal integrity testing, and root-cause debug of complex hardware and RTL issues.
• Develop production-ready test frameworks and automation tools using Python and C/C++ to validate high-speed interfaces, run PRBS testing, analyze eye diagrams, and measure jitter and link margins.
• Build and maintain multi-FPGA solutions including partitioning strategies, inter-FPGA communication protocols, clock distribution networks, and reset architectures.

Skills

SystemVerilog

RTL design

FPGA development

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Vivado

Python

C/C++

Oscilloscope/Scope

Job description

Synopsys, Inc. is seeking a senior FPGA/RTL design engineer to enable HAPS prototyping platforms. You will lead FPGA development, from RTL changes to timing closure and hardware validation on AMD/Xilinx devices, collaborating across hardware, software, and manufacturing teams.

You will build automation tools in Python/C++, validate high-speed interfaces, perform PRBS testing, and analyze eye diagrams, jitter, and link margins to ensure production-ready results.