Senior FPGA/ASIC Prototyping Applications Engineer

Synopsys; Mountain View (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Synopsys in Mountain View, CA is seeking an experienced Applications Engineer to support customer deployments of HAPS and ProtoCompiler across the ASIC-to-FPGA flow, including partitioning, synthesis, place-and-route, timing closure, and bring-up.

You will work with FPGA-based prototyping, interface IP such as PCIe, DDR, Ethernet, or AXI, and collaborate with R&D and sales to drive technical evaluations and deployments. Strong problem-solving, RTL, logs and timing analysis required.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 5-8 years in FPGA implementation, ASIC design, ASIC verification, FPGA prototyping, or applications engineering.
• Solid experience with FPGA synthesis, place-and-route, and timing closure using Xilinx Vivado, Intel Quartus, or similar tools.
• Working knowledge of SystemVerilog, RTL design, and verification concepts.
• Hands-on experience with at least one interface IP family such as PCIe, DDR, Ethernet, USB, or AXI.
• Scripting ability in Tcl, Python, or shell for automation and flow customization.
• Experience with Synopsys HAPS, ProtoCompiler, or other FPGA-based prototyping platforms is a strong plus.

Responsibilities

• Support customer deployments of HAPS and ProtoCompiler, working through the ASIC-to-FPGA flow including partitioning, synthesis, place-and-route, timing closure, and hardware bring-up
• Debug customer designs involving interface IP such as DDR4/DDR5, LPDDR, PCIe, Ethernet, USB, AXI, and other standard protocols
• Reproduce and analyze technical issues reported by customers, working with R&D to identify root causes and deliver solutions or workarounds
• Develop and document methodologies for partitioning strategies, clock architecture, debug instrumentation, and bring-up procedures
• Collaborate with Sales and Customer Success teams to support technical evaluations, proof-of-concept engagements, and deployment planning
• Use Verdi, ProtoCompiler runtime debug tools, and protocol analyzers to troubleshoot RTL, netlist, timing, and hardware issues

Skills

FPGA implementation

ASIC design

ASIC verification

FPGA prototyping

Applications engineering

Education

Bachelor's or Master's in Electrical/Computer Engineering or equivalent

Tools

Xilinx Vivado

Intel Quartus

Verdi

ProtoCompiler

HAPS

Job description

Synopsys in Mountain View, CA is seeking an experienced Applications Engineer to support customer deployments of HAPS and ProtoCompiler across the ASIC-to-FPGA flow, including partitioning, synthesis, place-and-route, timing closure, and bring-up.

You will work with FPGA-based prototyping, interface IP such as PCIe, DDR, Ethernet, or AXI, and collaborate with R&D and sales to drive technical evaluations and deployments. Strong problem-solving, RTL, logs and timing analysis required.