Senior FPGA Engineer for Space & Aerospace Systems

Cesiumastro; El Segundo (CA); Presencial; USD 140.000 - 168.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Stock options

Health, dental, vision

HSA/FSA

Retirement plans

Descripción de la vacante

CesiumAstro in El Segundo, CA is seeking a Senior FPGA Engineer to lead FPGA circuits and systems through all development phases for space and aerospace platforms. You will tackle HDL design and verification, high‑speed interfaces, multiple clock domains, and integration with digital processing cores, presenting results to customers and executive staff.

The ideal candidate has 6+ years in FPGA design (Verilog/VHDL) with lab experience and strong written and verbal communication.

Formación

• BS or MS in Electrical Engineering or Computer Engineering from an accredited university.
• At least 6 years of industry or university research experience in FPGA design/HDL implementations.
• Experience with FPGA design and verification (Verilog/VHDL).
• Hands-on lab experience with oscilloscopes, spectrum analyzers, RF signal generators, vector signal analyzers.
• Excellent written and verbal communication skills.

Responsabilidades

• Develop FPGA circuits and systems through all phases of the development process.
• Design, verify, test, and deploy FPGA solutions at the HDL level.
• Work on high‑speed serial interfaces, data streams, and multiple clock domains.
• Present engineering design reviews to customers and executive team; participate in proposals.

Conocimientos

Verilog/VHDL

FPGA design

HDL verification

High-speed interfaces

Digital signal processing

Educación

Bachelor of Science in Electrical Engineering

Master of Science in Electrical/Computer Engineering

Herramientas

Xilinx Vivado

Modelsim

HDL coder

Descripción del empleo

CesiumAstro in El Segundo, CA is seeking a Senior FPGA Engineer to lead FPGA circuits and systems through all development phases for space and aerospace platforms. You will tackle HDL design and verification, high‑speed interfaces, multiple clock domains, and integration with digital processing cores, presenting results to customers and executive staff.

The ideal candidate has 6+ years in FPGA design (Verilog/VHDL) with lab experience and strong written and verbal communication.