Senior FPGA Design & Verification Engineer – Versal On-Site

PDS Defense; El Segundo (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

PDS Defense in El Segundo, CA, seeks an experienced FPGA/ASIC designer to own top-level FPGA design, integrate third-party and in-house IP, update constraints, and oversee synthesis, timing closure, and Place & Route to ensure design integrity.

The role requires hands-on programming of Xilinx Versal, Ultrascale, and Ultrascale+ devices, collaboration with the systems engineering team for hardware/software integration, and on-site work in a secure environment.

Qualifications

• 5+ years FPGA/ASIC design experience.
• Experience with Versal family devices.
• Active U.S. security clearance.
• Bachelor degree in engineering, CS, math, physics or chemistry; ABET preferred.

Responsibilities

• Lead FPGA top-level design and integrate third-party and in-house IP cores.
• Update constraint files, perform synthesis, and ensure timing closure.
• Conduct Place & Route to validate design integrity.
• Collaborate with systems engineering for hardware/software integration; on-site work required.

Skills

FPGA design

ASIC design

Versal devices

Timing closure

Synthesis

Place & Route

Constraint files

Simulation

Security clearance

Education

Bachelor's degree in engineering/CS/math/physics/chemistry

Job description

PDS Defense in El Segundo, CA, seeks an experienced FPGA/ASIC designer to own top-level FPGA design, integrate third-party and in-house IP, update constraints, and oversee synthesis, timing closure, and Place & Route to ensure design integrity.

The role requires hands-on programming of Xilinx Versal, Ultrascale, and Ultrascale+ devices, collaboration with the systems engineering team for hardware/software integration, and on-site work in a secure environment.