Senior FPGA Design Engineer — Verilog & Timing (Versal)

Cts Technology Solutions, Inc.; El Segundo (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical plans

Dental & vision

401(k) + Roth

Paid holidays

Job summary

CTS Technology Solutions, Inc. seeks an Electronics Design and Analysis Engineer 3 to analyze requirements and develop architectures for electronic products, including HDL design and FPGA development (Versal/Ultrascale).

You will validate designs and support lifecycle engineering. The contractor will include FPGA top-level design, IP integration, synthesis, timing closure, and collaboration with system engineering for hardware/software integration.

Qualifications

• FPGA design experience required.
• Verilog/SystemVerilog HDL proficiency expected.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).
• Bachelor's degree in engineering or related field, ABET preferred.

Responsibilities

• Analyze customer and system requirements to develop architectures and detailed specifications for electronic products.
• Validate designs through reviews, testing and analysis to ensure compliance.
• Program FPGA devices (Versal/Ultrascale) and integrate third-party and in-house IP cores; perform synthesis and Place & Route.

Skills

FPGA design

Verilog/SystemVerilog

Vivado experience

Timing closure

HDL development

Education

Bachelor's degree in engineering or related field

ABET accreditation preferred

Tools

Xilinx Vivado

Job description

CTS Technology Solutions, Inc. seeks an Electronics Design and Analysis Engineer 3 to analyze requirements and develop architectures for electronic products, including HDL design and FPGA development (Versal/Ultrascale).

You will validate designs and support lifecycle engineering. The contractor will include FPGA top-level design, IP integration, synthesis, timing closure, and collaboration with system engineering for hardware/software integration.