FPGA Implementation Engineer 5 – Versal Onsite

Cts Technology Solutions, Inc.; El Segundo (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

CTS (the contractor) will lead FPGA/ASIC design projects in a 100% onsite setting in the United States, focusing on Verilog/SystemVerilog and Versal-based devices. The role requires a Secret clearance to start and involves updating constraints, synthesis, simulation, and Place & Route to ensure timing closure and design integrity.

The candidate will program FPGA devices primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families, and collaborate with system engineering for

Qualifications

• 5+ years FPGA/ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).
• Secret Clearance required.

Responsibilities

• Inherit FPGA top-level design and add new blocks and interfaces, integrate third-party and in-house IP cores.
• Update constraint files, perform synthesis, simulation, and Place & Route for timing closure and design integrity.
• Program FPGA devices, primarily Versal, Ultrascale, and Ultrascale+ families.
• Collaborate with system engineering to support hardware and software integration and testing.
• Produce high-quality technical documentation and deliver maintainable engineering solutions.
• On-site work required.

Skills

5+ years FPGA/ASIC design

Xilinx/AMD Vivado

Versal family devices

Verilog/SystemVerilog

FPGA implementation (synthesis, timing

Secret Clearance

Education

Bachelor's degree in engineering/related field

Advanced degree (MS/PhD) preferred

Tools

Xilinx Vivado

Job description

CTS (the contractor) will lead FPGA/ASIC design projects in a 100% onsite setting in the United States, focusing on Verilog/SystemVerilog and Versal-based devices. The role requires a Secret clearance to start and involves updating constraints, synthesis, simulation, and Place & Route to ensure timing closure and design integrity.

The candidate will program FPGA devices primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families, and collaborate with system engineering for