Senior FPGA Implementation Engineer - Versal/Xilinx Contract

Boeing Future of Flight; El Segundo (CA); Hybrid; USD 145,000 - 158,000; Part time

Job summary

Tundra Technical Solutions in the United States is seeking a contract FPGA/ASIC design engineer for a 6-month assignment. The role involves inheriting FPGA top-level design, integrating IP cores, updating constraints, and performing synthesis, simulation, and Place & Route to meet timing.

On-site work in El Segundo is required and candidates must have a US Secret clearance. Requirements include 5+ years FPGA/ASIC design, strong Xilinx Vivado experience, Versal devices, Verilog/SystemVerilog, and

Qualifications

• 5+ years of FPGA and/or ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).
• Active U.S. secret security clearance.

Responsibilities

• Inherit FPGA top-level design and add new functional blocks and interfaces, including integrating third-party and in-house IP cores.
• Update constraint files, perform synthesis, simulation, and Place & Route to ensure timing closure and design integrity.
• Program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families.
• Collaborate with the system engineering team to support hardware/software integration and testing; on-site work is required.

Skills

FPGA design

ASIC design

Verilog/SystemVerilog

Vivado

Security clearance

Timing closure

Synthesis

Education

Bachelor's degree

Job description

Tundra Technical Solutions in the United States is seeking a contract FPGA/ASIC design engineer for a 6-month assignment. The role involves inheriting FPGA top-level design, integrating IP cores, updating constraints, and performing synthesis, simulation, and Place & Route to meet timing.

On-site work in El Segundo is required and candidates must have a US Secret clearance. Requirements include 5+ years FPGA/ASIC design, strong Xilinx Vivado experience, Versal devices, Verilog/SystemVerilog, and