Senior FPGA Design Engineer - Versal & Secret Clearance

CTS International; El Segundo (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

CTS International in El Segundo, CA, seeks an FPGA/ASIC design contractor for a 100% onsite role requiring Secret Clearance. You will inherit FPGA top-level design, create new blocks and interfaces, integrate IP cores, update constraints, perform synthesis, simulation, and Place & Route to ensure timing closure, and program Versal/Ultrascale devices.

You will collaborate with the system engineering team to support hardware/software integration and testing, delivering a fully functioning system.

Qualifications

• 5+ years of FPGA and/or ASIC design experience.
• Experience with Xilinx/AMD Vivado and Versal family devices.
• Proficiency in Verilog/SystemVerilog and timing closure techniques.

Responsibilities

• Inherit FPGA top-level design and add new functional blocks and interfaces.
• Integrate third-party and in-house IP cores into the design.
• Update constraint files, perform synthesis, simulation, and Place & Route to ensure timing closure and design integrity.
• Program FPGA devices, primarily Versal, Ultrascale, and Ultrascale+.
• Collaborate with the system engineering team to support hardware/software integration and testing.

Skills

FPGA design

ASIC design

Verilog/SystemVerilog

Vivado

Timing closure

Synthesis & Place & Route

Versal/Ultrascale

Secret Clearance

Education

Bachelor's degree in engineering or related field

Job description

CTS International in El Segundo, CA, seeks an FPGA/ASIC design contractor for a 100% onsite role requiring Secret Clearance. You will inherit FPGA top-level design, create new blocks and interfaces, integrate IP cores, update constraints, perform synthesis, simulation, and Place & Route to ensure timing closure, and program Versal/Ultrascale devices.

You will collaborate with the system engineering team to support hardware/software integration and testing, delivering a fully functioning system.