Electrical Design and Analysis Engineer

PDS Defense; El Segundo (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

PDS Defense in El Segundo, CA, seeks an experienced FPGA/ASIC designer to own top-level FPGA design, integrate third-party and in-house IP, update constraints, and oversee synthesis, timing closure, and Place & Route to ensure design integrity.

The role requires hands-on programming of Xilinx Versal, Ultrascale, and Ultrascale+ devices, collaboration with the systems engineering team for hardware/software integration, and on-site work in a secure environment.

Qualifications

• 5+ years FPGA/ASIC design experience.
• Experience with Versal family devices.
• Active U.S. security clearance.
• Bachelor degree in engineering, CS, math, physics or chemistry; ABET preferred.

Responsibilities

• Lead FPGA top-level design and integrate third-party and in-house IP cores.
• Update constraint files, perform synthesis, and ensure timing closure.
• Conduct Place & Route to validate design integrity.
• Collaborate with systems engineering for hardware/software integration; on-site work required.

Skills

FPGA design

ASIC design

Versal devices

Timing closure

Synthesis

Place & Route

Constraint files

Simulation

Security clearance

Education

Bachelor's degree in engineering/CS/math/physics/chemistry

Job description

Will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families.

Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system. Therefore, on-site work is required.

Required Skills:

• 5+ years of FPGA and/or ASIC design experience;
• Experience with Versal family devices;
• Advanced FPGA implementation skills (synthesis, timing closure, constraints);
• Active U.S. security clearance

Education/experience

typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.