Senior FPGA Design & Analysis Engineer (Versal/Verilog)

The Adecco Group; El Segundo (CA); On-site; USD 131,000 - 164,000; Full time

Job summary

PDS Defense, Inc. in El Segundo, CA is seeking an Elect Design and Analy Engr 5 for FPGA/ASIC design work. The role focuses on FPGA top-level design, IP integration, synthesis, timing closure, and device programming, primarily Versal/UltraScale families.

The position requires on-site work in El Segundo, and candidates must hold an active U.S. security clearance. Ideal for engineers with strong digital hardware fundamentals and independent work style.

Qualifications

• 5+ years of FPGA and/or ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency required.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).
• Active U.S. security clearance

Responsibilities

• Inherit FPGA top-level design and create/add new blocks and interfaces including IP cores.
• Update constraint files and perform synthesis, simulation, and Place & Route to ensure timing closure.
• Program FPGA devices (Versal, UltraScale/UltraScale+) and verify design integrity.
• Collaborate with system engineering team for hardware/software integration and testing.
• On-site work is required.

Skills

FPGA/ASIC design

Vivado

Versal devices

Verilog/SystemVerilog

Timing closure

Active U.S. security clearance

Tools

Vivado

Job description

PDS Defense, Inc. in El Segundo, CA is seeking an Elect Design and Analy Engr 5 for FPGA/ASIC design work. The role focuses on FPGA top-level design, IP integration, synthesis, timing closure, and device programming, primarily Versal/UltraScale families.

The position requires on-site work in El Segundo, and candidates must hold an active U.S. security clearance. Ideal for engineers with strong digital hardware fundamentals and independent work style.