Senior ASIC/FPGA Verification Engineer IV

The Adecco Group; El Segundo (CA); On-site; USD 110,000 - 117,000; Full time

Job summary

PDS Defense, Inc. in El Segundo, CA is seeking an Electrical Design and Analysis Engineer 4 to advance state-of-the-art ASIC/FPGA verification. You will design verification environments and build self-checking testbenches, while collaborating with design and system engineers across multiple sites.

The role emphasizes SystemVerilog/UVM expertise, functional coverage, and regression-driven verification within a aerospace-focused product portfolio, including space and defense applications.

Qualifications

• Bachelor of Science in Engineering or equivalent non-US qualifications relevant to the job description.
• Experience in ASIC/FPGA verification processes and development of verification environments.
• Proficiency with SystemVerilog/UVM, including production design delivery and release.

Responsibilities

• Design and implement ASIC/FPGA verification environments using UVM and SystemVerilog.
• Develop self-checking and reusable test benches and associated drivers, monitors, predictors and scoreboards.
• Create Functional Coverage Models and perform Code Coverage analysis during simulation.
• Set up regression tests and collect coverage metrics to track progress.
• Assist in FPGA-based prototyping and validation per program requirements.
• Collaborate with cross-functional teams to align verification strategies with project goals and timelines.

Skills

SystemVerilog

UVM

Object-Oriented Programming

Testbenches

Functional Coverage

Code Coverage

Waveform Debug

Linux

Git

SVN

CVS

Education

Bachelor's degree in Engineering

Master's degree in EE/CE or related

Tools

Palladium

Git

SVN

CVS

Job description

PDS Defense, Inc. in El Segundo, CA is seeking an Electrical Design and Analysis Engineer 4 to advance state-of-the-art ASIC/FPGA verification. You will design verification environments and build self-checking testbenches, while collaborating with design and system engineers across multiple sites.

The role emphasizes SystemVerilog/UVM expertise, functional coverage, and regression-driven verification within a aerospace-focused product portfolio, including space and defense applications.