Senior FPGA/ASIC Co-Design Engineer

National MS Society; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

AMD in San Jose is seeking a hardware/FPGA design engineer to architect and implement high-performance ASIC/FPGA acceleration solutions, collaborating with architects and firmware teams. You will develop RTL in SystemVerilog/Verilog, verify complex logic, and lead pre-silicon verification and post-silicon bring-up across PCIe, CXL, Ethernet, and DDR5/6.

This role requires strong problem-solving, system-level validation, and scripting with Python/Tcl; you will work with global teams in a

Qualifications

• Hands-on experience with ASIC/FPGA design
• Expertise in SystemVerilog/Verilog, synchronous design and timing closure
• Knowledge of PCIe, AXI, DDR, Ethernet; familiarity with CXL/UAL
• Familiarity with UVM-based verification and emulation platforms (Palladium, Protium, Zebu)
• Hardware debugging experience
• Proficient in Python, Tcl, Makefiles, and Shell scripting

Responsibilities

• Participate in all phases of product development from architecture through implementation and validation
• Collaborate with architects and hardware/firmware engineers to implement features
• RTL Development: design, verify, and validate high-performance logic (PCIe Gen6/7, CXL, Ethernet, DDR)
• System Level Integration: integrate custom IP within AMD Vivado-based flows
• Pre-Si Verification: perform pre-silicon verification and emulation
• Post-Si Validation: lead Bring-up and debug complex hardware/software interactions

Skills

SystemVerilog/Verilog

Python

Tcl

Shell scripting

Education

Bachelors or Masters in Computer/Electrical Engineering

Tools

Palladium

Protium

Zebu

Vivado

Job description

AMD in San Jose is seeking a hardware/FPGA design engineer to architect and implement high-performance ASIC/FPGA acceleration solutions, collaborating with architects and firmware teams. You will develop RTL in SystemVerilog/Verilog, verify complex logic, and lead pre-silicon verification and post-silicon bring-up across PCIe, CXL, Ethernet, and DDR5/6.

This role requires strong problem-solving, system-level validation, and scripting with Python/Tcl; you will work with global teams in a