AI-Driven RTL Design & FPGA Integration Engineer

AMD; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

AMD in San Jose, CA is seeking a talented FPGA/RTL engineer to join the Adaptive & Embedded Computing Group. You will translate product concepts into RTL designs, collaborate with architects, hardware and software teams, and drive silicon implementation from concept to productization using modern EDA tools.

You will apply data-driven verification, support schedule and cost goals, and contribute to cross-timezone coordination across global teams while advancing cutting-edge FPAG architectures and

Qualifications

• Bachelor’s or Master’s in Computer Engineering or Electrical Engineering.
• Experience with RTL design and FPGA development.
• Familiarity with VLSI design flow and EDA tools.

Responsibilities

• Collaborate with architects and cross-functional teams to define IP features and requirements.
• Develop RTL designs and silicon/prototyping plans from conception to productization.
• Refine AI-driven automation to accelerate IP integration and development timelines.
• Support functional simulation and verification to ensure robust validation.

Skills

RTL design

Verilog/SystemVerilog

VLSI design flow

FPGA architecture

Scripting (Python/Perl/Tcl)

Cross-functional collaboration

Communication skills

Education

Bachelor's or Master’s in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Primetime

VCS

Cadence Virtuoso

Job description

AMD in San Jose, CA is seeking a talented FPGA/RTL engineer to join the Adaptive & Embedded Computing Group. You will translate product concepts into RTL designs, collaborate with architects, hardware and software teams, and drive silicon implementation from concept to productization using modern EDA tools.

You will apply data-driven verification, support schedule and cost goals, and contribute to cross-timezone coordination across global teams while advancing cutting-edge FPAG architectures and