Senior ASIC/FPGA Design Engineer - RTL to GDS

Advanced Micro Devices, Inc.; San Jose (CA); Hybrid; USD 150,000 - 190,000; Full time

Benefits offered by this job

AMD Benefits at a glance

Job summary

Advanced Micro Devices, Inc. in San Jose, CA is seeking a hardware design engineer to contribute to FPGA product development within the AECG group.

You will participate in RTL development, implement complex digital and mixed-signal blocks, and collaborate with cross-functional teams across time zones to deliver silicon and software solutions. The role requires strong Verilog/SystemVerilog RTL experience, proficiency with UVM-based verification, and scripting in Python/Perl/Tcl/Shell.

Qualifications

• Bachelor's or Master's degree in computer engineering, electrical engineering, or related field.
• Strong RTL design using Verilog/SystemVerilog.
• Experience with UVM-based verification.
• Proficiency in scripting languages (Python, Perl, Tcl, Shell).
• Excellent written and verbal English; cross-functional collaboration.

Responsibilities

• Participate in RTL development through GDS implementation.
• Design RTL for digital and mixed-signal blocks using Verilog and SystemVerilog.
• Support physical design activities: synthesis, DFT, place-and-route, STA.
• Collaborate with Verification teams for block-level verification using SystemVerilog/UVM.
• Develop/design automation tooling with Perl, Tcl, Shell, Python.
• Partner with cross-functional teams across locations.
• Communicate with global project teams to meet milestones.

Skills

Verilog

SystemVerilog

RTL design

UVM

Python

Perl

Tcl

Shell scripting

Education

Bachelor's or Master's degree in electrical/computer engineering or related field

Tools

Synopsys DC Compiler

Primetime

VCS

Cadence Virtuoso

Job description

Advanced Micro Devices, Inc. in San Jose, CA is seeking a hardware design engineer to contribute to FPGA product development within the AECG group.

You will participate in RTL development, implement complex digital and mixed-signal blocks, and collaborate with cross-functional teams across time zones to deliver silicon and software solutions. The role requires strong Verilog/SystemVerilog RTL experience, proficiency with UVM-based verification, and scripting in Python/Perl/Tcl/Shell.