FPGA Solutions Architect — Hardware-Software Co-Design

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD is seeking an experienced FPGA/SoC architect to design and implement high-performance hardware and software co-design solutions for FPGA-based acceleration across various applications. You will develop RTL with SystemVerilog/Verilog and embedded firmware for ARM Cortex (APU/RPU) or RISC-V cores, and integrate IP using Vivado/Vitis.

You will collaborate with cross-functional teams, perform pre- and post-silicon validation, and drive Bring-up activities in a fast-paced, global environment.

Qualifications

• Bachelor's or master's degree in computer engineering or Electrical Engineering.
• Hands-on FPGA experience.
• Strong C/C++ for bare-metal or RTOS on ARM/RISC-V cores.
• Linux kernel driver development experience is a strong plus.
• Familiarity with PCIe, AXI, DDR, and Ethernet.
• Familiarity with CXL or UAL is highly desirable.
• Proficiency in Python, Tcl, Makefiles, and shell scripting.

Responsibilities

• Participate in architectural design and development across the product lifecycle from exploration to validation and productization.
• Collaborate with architects, hardware and firmware engineers to define features.
• RTL Development: design/verify/validate SystemVerilog/Verilog for PCIe, CXL, UAL, Ethernet, DDR5/6.
• Embedded System Development: develop firmware and low-level system software for ARM Cortex (APU/RPU) or RISC-V cores.
• System Level Integration: use Vivado/Vitis to integrate IP with NoC, memory and subsystems.
• Pre-Si Verification: perform pre-silicon verification and emulation.
• Post-Si Validation: lead bring-up and debug interactions between firmware, IPs, and FPGA fabric.

Skills

FPGAs

SystemVerilog

C/C++

Embedded firmware

Linux kernel driver

IPC/DMA

ARM/RISC-V

Education

Bachelor's or Master's in CE/EE

Tools

Vivado

Vitis

Python

Makefiles

Shell scripting

Job description

AMD is seeking an experienced FPGA/SoC architect to design and implement high-performance hardware and software co-design solutions for FPGA-based acceleration across various applications. You will develop RTL with SystemVerilog/Verilog and embedded firmware for ARM Cortex (APU/RPU) or RISC-V cores, and integrate IP using Vivado/Vitis.

You will collaborate with cross-functional teams, perform pre- and post-silicon validation, and drive Bring-up activities in a fast-paced, global environment.