Design Verification Engineer for High-Performance ASICs

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD in Santa Clara, CA is seeking an adaptive Design Verification Engineer to join our growing team. You will drive verification for complex processor IP, collaborating with RTL, firmware, and silicon teams across time zones to deliver high-quality products.

The role emphasizes Verilog/SystemVerilog/UVM, C/C++, and memory/DDR verification experience, with a focus on directed and random tests, code coverage, and rigorous debugging. On-site work preferred.

Qualifications

• Experience with Verilog/SystemVerilog and modern verification libraries like UVM.
• Experience with C/C++.
• Strong ASIC design verification experience.
• Experience/Background with DDR or Memory Controller; PHY verification is a plus.
• Experience with scripting languages like Python, Perl and TCL is a plus.

Responsibilities

• Develop/Maintain tests for functional verification.
• Build directed and random verification tests, debug test failures to determine root cause, work with RTL and firmware engineers to resolve design defects and test issues.
• Work on functional & code coverage verification.
• Provide technical support to other teams.

Skills

Verilog

SystemVerilog

UVM

C/C++

ASIC design verification

Memory/DDR controller

Python

Perl

TCL

Education

Bachelor's or Master's or Ph.D. in Computer/Electrical Engineering

Job description

AMD in Santa Clara, CA is seeking an adaptive Design Verification Engineer to join our growing team. You will drive verification for complex processor IP, collaborating with RTL, firmware, and silicon teams across time zones to deliver high-quality products.

The role emphasizes Verilog/SystemVerilog/UVM, C/C++, and memory/DDR verification experience, with a focus on directed and random tests, code coverage, and rigorous debugging. On-site work preferred.