Senior FPGA Architect for AI-Driven Hardware

Jobs Paloaltonetworks; California; On-site; USD 156,000 - 253,000; Full time

Job summary

Palo Alto Networks is seeking an experienced FPGA/ASIC design engineer to own architecture, RTL, timing closure, and lab bring-up for high‑performance firewall platforms. You will collaborate with software and hardware teams to deliver silicon for next‑generation devices.

You’ll synthesize using Vivado/Quartus, verify with FPGA prototyping, and optimize resources while integrating IP blocks such as PCIe, Ethernet, and memory controllers. Strong SystemVerilog & debugging skills are required.

Qualifications

• BS in EE, CE, or CS; MS preferred.
• 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
• Expert SystemVerilog and Verilog RTL development for FPGA/CPLD architectures.
• Proven timing closure across multi-clock domains.
• Scripting proficiency: Python, C/C++, Perl, bash or tcsh.
• Integrating high-speed IP cores (PCIe Gen4/5/6, QDMA, Ethernet MAC/PHY, memory controllers).
• FPGA rapid prototyping, in-system debugging (ILA, SignalTap) and lab bring-up.
• Resource utilization optimization and timing closure strategies.
• Analyzing timing, power, and area reports and driving fixes.
• Proficiency with AI tools integrated into hardware design/verification workflows.
• Excellent leadership, collaboration, and written/verbal communication.

Responsibilities

• Write comprehensive micro-architecture and functional specifications for FPGA, CFPGA, and CPLD designs.
• Design high-quality SystemVerilog/Verilog RTL targeted for advanced FPGA architectures meeting timing/power/area targets.
• Synthesize & Implement designs using Vivado, Quartus, and Synopsys tools, achieving multi-clock timing closure and resource optimization.
• Prototype & Validate ASIC designs on FPGA platforms, executing lab bring‑up, in-system debugging, and hardware validation.
• Collaborate with software and platform teams to define interfaces, review memory map structures, and integrate complex IP blocks (PCIe, Ethernet, QDMA, DDR/LPDDR).
• Innovate: pilot AI‑driven design or verification flows that cut schedule risk.

Skills

SystemVerilog

Verilog RTL

FPGA design

Scripting (Python/C/C++)

PCIe Gen4/5/6

Lab bring-up / in-system debug

Timing closure

ASIC/FPGA prototyping

Team leadership

Strong communication

Education

BS in EE/CE/CS

MSEE or equivalent experience

Tools

Vivado

Quartus

Synopsys tools

Job description

Palo Alto Networks is seeking an experienced FPGA/ASIC design engineer to own architecture, RTL, timing closure, and lab bring-up for high‑performance firewall platforms. You will collaborate with software and hardware teams to deliver silicon for next‑generation devices.

You’ll synthesize using Vivado/Quartus, verify with FPGA prototyping, and optimize resources while integrating IP blocks such as PCIe, Ethernet, and memory controllers. Strong SystemVerilog & debugging skills are required.