Sr FPGA Design Engineer (NetSec)

Jobs Paloaltonetworks; California; Presencial; USD 156.000 - 253.000; Jornada completa

Descripción de la vacante

Palo Alto Networks is seeking an experienced FPGA/ASIC design engineer to own architecture, RTL, timing closure, and lab bring-up for high‑performance firewall platforms. You will collaborate with software and hardware teams to deliver silicon for next‑generation devices.

You’ll synthesize using Vivado/Quartus, verify with FPGA prototyping, and optimize resources while integrating IP blocks such as PCIe, Ethernet, and memory controllers. Strong SystemVerilog & debugging skills are required.

Formación

• BS in EE, CE, or CS; MS preferred.
• 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
• Expert SystemVerilog and Verilog RTL development for FPGA/CPLD architectures.
• Proven timing closure across multi-clock domains.
• Scripting proficiency: Python, C/C++, Perl, bash or tcsh.
• Integrating high-speed IP cores (PCIe Gen4/5/6, QDMA, Ethernet MAC/PHY, memory controllers).
• FPGA rapid prototyping, in-system debugging (ILA, SignalTap) and lab bring-up.
• Resource utilization optimization and timing closure strategies.
• Analyzing timing, power, and area reports and driving fixes.
• Proficiency with AI tools integrated into hardware design/verification workflows.
• Excellent leadership, collaboration, and written/verbal communication.

Responsabilidades

• Write comprehensive micro-architecture and functional specifications for FPGA, CFPGA, and CPLD designs.
• Design high-quality SystemVerilog/Verilog RTL targeted for advanced FPGA architectures meeting timing/power/area targets.
• Synthesize & Implement designs using Vivado, Quartus, and Synopsys tools, achieving multi-clock timing closure and resource optimization.
• Prototype & Validate ASIC designs on FPGA platforms, executing lab bring‑up, in-system debugging, and hardware validation.
• Collaborate with software and platform teams to define interfaces, review memory map structures, and integrate complex IP blocks (PCIe, Ethernet, QDMA, DDR/LPDDR).
• Innovate: pilot AI‑driven design or verification flows that cut schedule risk.

Conocimientos

SystemVerilog

Verilog RTL

FPGA design

Scripting (Python/C/C++)

PCIe Gen4/5/6

Lab bring-up / in-system debug

Timing closure

ASIC/FPGA prototyping

Team leadership

Strong communication

Educación

BS in EE/CE/CS

MSEE or equivalent experience

Herramientas

Vivado

Quartus

Synopsys tools

Descripción del empleo

Our Mission

At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting‑edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you’re ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you’re in the right place.

Who We Are

In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values: Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real-world problems and ideating beside the best and the brightest, we invite you to join us!

We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real‑time problem‑solving, stronger relationships, and the kind of precision that drives great outcomes.

Job Summary

About the RoleJoin our FPGA engineering team and help deliver high‑performance digital logic, CPLD/CFPGA modules, and hardware acceleration platforms for our next‑generation firewalls. You will own FPGA design from architecture and specification through RTL, timing closure, synthesis, and lab bring‑up, collaborating closely with cross‑functional software, hardware, and verification teams.

What You’ll Do

• Write comprehensive micro‑architecture and functional specifications for FPGA, CFPGA, and CPLD designs.


• Design high‑quality SystemVerilog/Verilog RTL targeted for advanced FPGA architectures (AMD/Xilinx, Altera/Intel) meeting strict timing, power, and area targets.


• Synthesize & Implement designs using Vivado, Quartus, and Synopsys tools, achieving multi‑clock timing closure and resource optimization.


• Prototype & Validate ASIC designs on FPGA platforms, executing lab bring‑up, in‑system debugging, and hardware validation.


• Collaborate with software and platform teams to define interfaces, review memory map structures, and integrate complex IP blocks (PCIe, Ethernet, QDMA, DDR/LPDDR).


• Innovate: pilot AI‑driven design or verification flows that cut schedule risk.

Qualifications

Required Qualifications

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred).


• 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.


• Expert SystemVerilog and Verilog RTL development skills for FPGA and CPLD architectures.


• Proven track record of FPGA synthesis, placement, routing, and static timing analysis (STA) closure across multi‑clock domains.


• Scripting proficiency (Python, C/C++, Perl, bash or tcsh).


• Demonstrated strength in:
  
  
  • Integrating and configuring high-speed IP cores (e.g., PCIe Gen4/5/6, QDMA, Ethernet MAC/PHY, memory controllers).
  
  
  • FPGA rapid prototyping, in-system logic debugging (ILA, SignalTap), and lab bring‑up.
  
  
  • Optimizing resource utilization (LUTs, FFs, BRAM/URAM, DSP blocks) and timing closure strategies.
  
  
  • Analyzing timing, power, and area reports and driving fixes.
  
  
  • Demonstrated proficiency or active experience integrating modern AI tools (e.g., LLM coding assistants, automated test generators, or ML‑enhanced EDA features) into hardware design, scripting, or verification workflows.
  
  


• Excellent leadership, collaboration, and written/verbal communication.

Preferred / Nice-to-Have

• Experience with ASIC-to-FPGA prototyping flows and emulation environments.


• Hands‑on experience with high‑density FPGA platforms (AMD UltraScale+, Altera Agilex/Stratix).


• Formal verification techniques (e.g., VC Formal) applied to FPGA module verification.


• Networking protocol experience (Ethernet, eDSA, IPsec, packet processing) and CPLD/CFPGA board‑management logic design.

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non‑sales roles) or base salary + commission target (for sales/com‑missioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here.

$156,400.00 - $253,000.00/yr

Our Commitment

We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at [e-mail].

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation or other legally protected characteristics.

All your information will be kept confidential according to EEO guidelines.

Is role eligible for Immigration Sponsorship?: Yes