Senior FPGA Design Engineer: AI-Driven Hardware

Palo Alto Networks, Inc.; California; On-site; USD 156,000 - 253,000; Full time

Job summary

Palo Alto Networks, Inc. is seeking an experienced FPGA engineer to own digital logic design for high-performance firewalls.

You will lead architecture, RTL implementation, timing closure, and lab bring-up, collaborating with software, hardware, and verification teams. You will synthesize using Vivado, Quartus, and Synopsys, prototype on FPGA platforms, and drive IP integration (PCIe, Ethernet, memory controllers).

Qualifications

• BS in EE, CE or CS; MSEE or equivalent experience preferred.
• 10+ years front-end ASIC design ownership with production experience.
• Expert SystemVerilog/Verilog RTL for FPGA/CPLD; multi-clock timing closure.

Responsibilities

• Write specs for FPGA, CPLD designs and interfaces.
• Design RTL for FPGA architectures, meet timing/power/area targets.
• Synthesize & implement using Vivado, Quartus, Synopsys; achieve timing closure.
• Prototype and validate ASIC designs on FPGA platforms; lab bring-up.
• Collaborate to define interfaces and integrate IP blocks (PCIe, Ethernet, DDR).
• Pilot AI-driven design/verification flows to reduce schedule risk.

Skills

SystemVerilog

Verilog RTL

FPGA design

CPLD architectures

ASIC design ownership

Synthesis/Timing closure

Python

C/C++

Perl

Bash

PCIe Gen4/5/6

QDMA

Ethernet

Memory controllers

ILA/SignalTap

AI tools in hardware

Team leadership

Education

BS in EE/CE/CS

Tools

Vivado

Quartus

Synopsys

ILA

SignalTap

Job description

Palo Alto Networks, Inc. is seeking an experienced FPGA engineer to own digital logic design for high-performance firewalls.

You will lead architecture, RTL implementation, timing closure, and lab bring-up, collaborating with software, hardware, and verification teams. You will synthesize using Vivado, Quartus, and Synopsys, prototype on FPGA platforms, and drive IP integration (PCIe, Ethernet, memory controllers).