Senior ASIC Design Engineer – AI‑Driven Silicon Bring‑Up

Palo Alto Networks, Inc.; Santa Clara (CA); On-site; USD 156,000 - 253,000; Full time

Job summary

Palo Alto Networks, Inc. is seeking an experienced ASIC design professional to own frontend design from spec to silicon bring-up for our next‑gen firewall platforms.

You will work with verification and physical‑design teams to hit aggressive performance, power, and schedule goals. Responsibilities include writing micro-architecture specs, creating SystemVerilog RTL, and verifying blocks through simulation, emulation, and formal methods, with a focus on robust, scalable designs.

Qualifications

• BS in EE, CE, or CS; MS preferred.
• 10+ years front-end ASIC design ownership shipping 2+ chips
• Expert SystemVerilog RTL skills
• Proven track record in selecting and configuring complex IP blocks for high-speed interfaces (PCIe, Ethernet, DDR)
• Scripting proficiency: Python, C/C++, Perl, shell
• Strengths in micro-architecture from high-level requirements and datapath design
• Debugging across simulation, emulation, and silicon
• Excellent leadership, collaboration, and communication

Responsibilities

• Write clear design and micro-architecture specifications.
• Design SystemVerilog RTL that meets area, performance, and power targets.
• Verify your blocks with simulation, emulation, formal methods, and silicon bring-up.
• Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features.
• Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability.
• Innovate: pilot AI-driven design or verification flows that cut schedule risk.

Skills

SystemVerilog RTL

IP blocks selection/configuration

Scripting (Python/C/C++/Perl/bash/tcsh

Micro-architecture definition

Datapath design

Debugging across sim/emu/silicon

Leadership & communication

Education

BS in EE, CE, or CS

Tools

PCIe

Ethernet

DDR

Job description

Palo Alto Networks, Inc. is seeking an experienced ASIC design professional to own frontend design from spec to silicon bring-up for our next‑gen firewall platforms.

You will work with verification and physical‑design teams to hit aggressive performance, power, and schedule goals. Responsibilities include writing micro-architecture specs, creating SystemVerilog RTL, and verifying blocks through simulation, emulation, and formal methods, with a focus on robust, scalable designs.