Senior ASIC Emulation Engineer — Pre-Silicon FPGA Prototyping

Palo Alto Networks; Santa Clara (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Palo Alto Networks is seeking a Senior/Lead ASIC Emulation Engineer to drive execution, verification, and validation of high-complexity network security processors on state-of-the-art emulation and FPGA prototyping platforms. You will bridge pre-silicon hardware design, firmware/software development, and post-silicon validation, shaping next-generation firewall performance.

You will define emulation architecture, build scalable co-emulation environments, and accelerate software bring-up while

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 8+ years of hands-on experience in hardware emulation, FPGA prototyping, and ASIC verification, with a proven track record of shipping complex SoCs to production.
• Expertise with at least one major emulation platform (Cadence Palladium, Synopsys ZeBu, or Siemens Veloce).
• Strong mastery of SystemVerilog, Verilog, C/C++, and UVM/DPI interfaces.
• Proficiency with platform debug tools (SimVision, Indago, Verdi, waveform probes, and dynamic memory readback).
• Experience developing or integrating transactors, speed adapters, and virtual/physical interfaces (e.g., PCIe, Ethernet, DDR, CXL).
• Advanced scripting skills in Python, Tcl, Perl, and UNIX shell to automate compilation, regression, and build infrastructure.

Responsibilities

• Architect, bring up, and maintain enterprise-scale hardware emulation platforms (e.g., Palladium, ZeBu, Veloce).
• Collaborate with ASIC Architecture, Design, Verification, and Software/Firmware teams to define pre-silicon emulation plans and timelines.
• Compile, synthesize, and fit multi-million/billion-gate SoC designs onto emulation hardware with power, timing, and capacity optimization.
• Develop transactors, rate adapters, speed adapters, and hybrid interfaces to connect emulation models with host software testbenches and real-world traffic.
• Enable pre-silicon software development and OS/driver bring-up by executing real-world workloads on the emulator.
• Debug complex hardware/firmware/protocol failures using advanced emulation debug features.
• Automate build, deployment, triage, and regression flows using Python, Tcl, and CI/CD pipelines.
• Partner with post-silicon validation teams to reproduce and triage silicon anomalies on the emulation platform.

Skills

Hardware emulation

FPGA prototyping

ASIC verification

SystemVerilog

Verilog

C/C++

UVM/DPI interfaces

Python scripting

CI/CD pipelines

Education

BS/MS in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence Palladium

Synopsys ZeBu

Siemens Veloce

Job description

Palo Alto Networks is seeking a Senior/Lead ASIC Emulation Engineer to drive execution, verification, and validation of high-complexity network security processors on state-of-the-art emulation and FPGA prototyping platforms. You will bridge pre-silicon hardware design, firmware/software development, and post-silicon validation, shaping next-generation firewall performance.

You will define emulation architecture, build scalable co-emulation environments, and accelerate software bring-up while