Lead FPGA Design Engineer - AI-Driven Hardware

Palo Alto Networks, Inc.; Santa Clara (CA); On-site; USD 156,000 - 253,000; Full time

Job summary

Palo Alto Networks, Inc. is seeking an experienced FPGA/ASIC engineer to own the design from architecture through RTL and timing closure. You will work with cross-functional teams to deliver high-performance FPGA platforms for next‑generation firewalls.

The role emphasizes SystemVerilog/Verilog RTL, Synthesis with Vivado/Quartus/Synopsys, and lab bring-up on FPGA platforms. Collaboration and leadership are essential for success.

Qualifications

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
• 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
• Expert SystemVerilog and Verilog RTL development skills.
• Proven track record of FPGA synthesis, placement, routing, and STA closure across multi-clock domains.
• Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
• Demonstrated strength in integrating high-speed IP cores (PCIe Gen4/5/6, QDMA, Ethernet MAC/PHY).
• FPGA rapid prototyping, in-system logic debugging, and lab bring-up.
• Optimizing resource utilization and timing closure strategies.
• Experience integrating AI tools into hardware design/verification workflows.
• Excellent leadership, collaboration, and communication.

Responsibilities

• Write comprehensive micro-architecture and functional specs for FPGA/CPLD/CFPGA designs.
• Design SystemVerilog/Verilog RTL for FPGA architectures meeting timing/power/area targets.
• Synthesize and implement designs using Vivado, Quartus, and Synopsys tools.
• Prototype and validate ASIC designs on FPGA platforms with lab bring-up.
• Collaborate with software and platform teams to define interfaces and memory maps.
• Pilot AI-driven design or verification flows to reduce schedule risk.

Skills

SystemVerilog

Verilog RTL

Python

C/C++

Perl

Bash

PCIe Gen4/5/6

FPGA prototyping

in-system debugging

Leadership

Education

BS in EE/CE/CS

MS in EE or equivalent (preferred)

Tools

Vivado

Quartus

Synopsys

Job description

Palo Alto Networks, Inc. is seeking an experienced FPGA/ASIC engineer to own the design from architecture through RTL and timing closure. You will work with cross-functional teams to deliver high-performance FPGA platforms for next‑generation firewalls.

The role emphasizes SystemVerilog/Verilog RTL, Synthesis with Vivado/Quartus/Synopsys, and lab bring-up on FPGA platforms. Collaboration and leadership are essential for success.