Senior ASIC Design Architect – AI/LLM Networking Chips

Fortinet, Inc.; Sunnyvale (CA); On-site; USD 192,000 - 235,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Life insurance

Disability insurance

401(k)

Annual leave

Job summary

Fortinet is seeking an experienced ASIC Designer in Sunnyvale to join the R&D team and help architect FortiASIC technology for high-performance network security systems.

This role covers RTL implementation, verification, IP integration, and bring-up across the full design lifecycle, including FPGA prototyping and system-level debugging. Requires 8+ years, Verilog/SystemVerilog, UVM, and AI/LLM/NPU background.

Qualifications

• 8+ years of experience in high-performance networking or processor design.
• Proven track record of taking complex ASIC/FPGA designs from concept to mass production.
• Hands-on Verilog/SystemVerilog HDL coding, synthesis, and design verification.
• Lifecycle experience from specification drafting through system bring-up.
• Strong SystemVerilog and UVM verification methodologies.
• Strong background in AI/LLM accelerator or NPU design.
• Strong problem-solving skills and strong written/verbal communication.

Responsibilities

• Micro-Architecture: Define and refine the micro-architecture of FortiASICs.
• Verification & Coverage: Review test plans, analyze coverage, and run full-chip simulations.
• RTL & Design Implementation: Implement designs in SystemVerilog/Verilog; perform lint/CDC reviews, synthesis, timing analysis, and IP integration.
• Physical Design & PPA: Verify constraints, optimize placement and routing, close timing, and optimize power, performance, area.
• FPGA Prototyping: Emulate/prototype designs on FPGAs for complete debug and validation cycles.
• Bring-Up & Support: System/board bring-up, post-silicon debugging, ongoing technical support.
• Execution & Collaboration: Self-starter with strong teamwork across cross-functional engineering.

Skills

8+ years experience

Verilog/SystemVerilog

UVM verification

AI/LLM accelerator

NPU design

Networking knowledge

Cross-functional collaboration

Education

B.S./M.S. in EE/CE/CS

Tools

Altera/Intel FPGA

AMD Xilinx FPGA

Job description

Fortinet is seeking an experienced ASIC Designer in Sunnyvale to join the R&D team and help architect FortiASIC technology for high-performance network security systems.

This role covers RTL implementation, verification, IP integration, and bring-up across the full design lifecycle, including FPGA prototyping and system-level debugging. Requires 8+ years, Verilog/SystemVerilog, UVM, and AI/LLM/NPU background.