Senior ASIC Design Engineer - AI-Driven SoCs

Jobs Paloaltonetworks; California; Vor Ort; USD 156.000 - 253.000; Vollzeit

Zusammenfassung

Palo Alto Networks is seeking an experienced ASIC Design Lead to own frontend design from specification to silicon bring-up for next-generation firewall platforms. You will work with verification and physical-design teams to hit aggressive performance, power, and schedule goals.

The role requires 10+ years of ASIC frontend design ownership, expert SystemVerilog RTL skills, and a track record shipping chips to mass production.

Qualifikationen

• BS in EE, CE, or CS; MS preferred.
• 10+ years' front-end ASIC design ownership and shipping 2+ chips to mass production.
• Expert SystemVerilog RTL skills.
• Experience selecting, integrating IP blocks for PCIe, Ethernet, or DDR.
• Scripting proficiency: Python, C/C++, Perl, Bash or tcsh.
• Strong leadership, collaboration, and written/verbal communication.

Aufgaben

• Write design and micro-architecture specifications.
• Design SystemVerilog RTL meeting area, performance, and power targets.
• Verify blocks with simulation, emulation, formal methods, and silicon bring-up.
• Collaborate with verification engineers to debug scenarios, close coverage.
• Partner with physical-design teams to review reports and optimize RTL.
• Pilot AI-driven design or verification flows to reduce schedule risk.

Kenntnisse

SystemVerilog RTL

ASIC design ownership

Leadership

Collaboration

Debugging

Ausbildung

BS in EE/CE/CS

Tools

Python

C/C++

Perl

Bash/tcsh

Jobbeschreibung

Palo Alto Networks is seeking an experienced ASIC Design Lead to own frontend design from specification to silicon bring-up for next-generation firewall platforms. You will work with verification and physical-design teams to hit aggressive performance, power, and schedule goals.

The role requires 10+ years of ASIC frontend design ownership, expert SystemVerilog RTL skills, and a track record shipping chips to mass production.