Senior ASIC Design Engineer — AI-Driven Firewall Silicon

Palo Alto Networks; Santa Clara (CA); On-site; USD 156,000 - 253,000; Full time

Job summary

Palo Alto Networks in Santa Clara, CA, is seeking an experienced ASIC design lead to own frontend design from specification through silicon bring-up. You will work with verification and physical-design teams to hit aggressive performance, power, and schedule goals.

The role requires 10+ years' front-end ASIC design ownership, expert SystemVerilog RTL skills, and proven ability to integrate IP blocks for PCIe, Ethernet, or DDR. This position offers strong growth and competitive compensation.

Qualifications

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
• 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
• Expert SystemVerilog RTL skills.
• Proven track record of selecting, integrating, and configuring complex IP blocks for high-speed interfaces such as PCIe, Ethernet, or DDR.

Responsibilities

• Write clear design and micro-architecture specifications.
• Design SystemVerilog RTL that meets area, performance, and power targets.
• Verify your blocks with simulation, emulation, formal methods, and silicon bring-up.
• Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features.
• Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability.
• Innovate: pilot AI-driven design or verification flows that cut schedule risk.

Skills

SystemVerilog RTL

Python scripting

C/C++

Education

BS in EE, CE, or CS

10+ years front-end ASIC design ownership

Job description

Palo Alto Networks in Santa Clara, CA, is seeking an experienced ASIC design lead to own frontend design from specification through silicon bring-up. You will work with verification and physical-design teams to hit aggressive performance, power, and schedule goals.

The role requires 10+ years' front-end ASIC design ownership, expert SystemVerilog RTL skills, and proven ability to integrate IP blocks for PCIe, Ethernet, or DDR. This position offers strong growth and competitive compensation.