Senior Fabric & NoC Verification Engineer — Equity

NVIDIA; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Job summary

NVIDIA in Santa Clara, CA is seeking a Senior Custom SOC/IP Verification Engineer to verify next-generation SoCs and IPs, focusing on fabric and interconnect verification across IP and full-chip integration.

You will design and implement UVM-based testbenches, collaborate with Architecture, SW/FW, Design, and Validation teams, and drive verification strategies for high-performance interconnect subsystems.

Qualifications

• Requires a B.S./M.S. in Computer or Electrical Engineering or equivalent.
• 5+ years in ASIC verification with fabric/interconnect focus at IP and SoC levels.
• Strong SystemVerilog and UVM knowledge.
• Experience with interconnect protocols and NoC architectures.

Responsibilities

• Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and implement test plans for fabric and interconnect verification of SoCs using UVM-based environments, targeting both IP-level and system-level scenarios.
• Design and implement constrained-random and directed SystemVerilog testbenches targeting interconnect fabrics, network-on-chip (NoC) topologies, and multi-agent SoC integrations.
• Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.
• Drive the development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

Skills

SystemVerilog

UVM

Python

Perl

TCL

AMBA AXI

CHI

NoC topologies

SoC interconnect verification

Education

Bachelor's/Master's in Computer or Electrical Engineering

Job description

NVIDIA in Santa Clara, CA is seeking a Senior Custom SOC/IP Verification Engineer to verify next-generation SoCs and IPs, focusing on fabric and interconnect verification across IP and full-chip integration.

You will design and implement UVM-based testbenches, collaborate with Architecture, SW/FW, Design, and Validation teams, and drive verification strategies for high-performance interconnect subsystems.