Senior Custom SOC/IP Verification Architect - Equity

NVIDIA; Austin (TX); On-site; USD 180,000 - 300,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify next‑gen SoC and IP solutions in Austin, TX. The role emphasizes fabric and interconnect verification across IP and full‑chip integration with SystemVerilog and UVM expertise.

You will develop test plans, build constrained‑random and directed testbenches, and collaborate with Architecture, SW/HW, and Validation teams to ensure first‑time-right verification and robust strategies.

Qualifications

• BS or MS in Computer/Electrical Engineering or equivalent experience.
• 6+ years of ASIC verification experience focusing on fabric/interconnect or NoC verification at IP and full chip levels.
• Strong SystemVerilog and UVM knowledge.
• Hands-on experience with bus protocols (AMBA AXI, CHI) and understanding of ordering, coherency, and flow control.

Responsibilities

• Verify ASIC fabric and interconnect IP blocks and full-chip integration (DMA, routing, arbitration, ordering, flow control).
• Develop and implement test plans for fabric/interconnect verification in UVM environments at IP and system level.
• Create constrained-random and directed SystemVerilog testbenches for interconnect fabrics and NoC topologies.
• Collaborate with Architecture, SW/HW, Design, Modeling, Emulation, and Post‑Silicon Validation teams.
• Drive silicon/platform verification strategies for fabric and interconnect subsystems.

Skills

SystemVerilog

UVM

Fabric verification

Interconnect verification

Python

Perl

TCL

AMBA AXI

CHI

NoC topologies

Multi-initiator/multi-target intercon

SoC verification

Education

B.S. or M.S. in Computer/Electrical Engineering (or equivalent)

Tools

SystemVerilog/UVM

Job description

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify next‑gen SoC and IP solutions in Austin, TX. The role emphasizes fabric and interconnect verification across IP and full‑chip integration with SystemVerilog and UVM expertise.

You will develop test plans, build constrained‑random and directed testbenches, and collaborate with Architecture, SW/HW, and Validation teams to ensure first‑time-right verification and robust strategies.