Custom SOC IP Verification Engineer

NVIDIA; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Job summary

NVIDIA in Santa Clara, CA is seeking a Senior Custom SOC/IP Verification Engineer to verify next-generation SoCs and IPs, focusing on fabric and interconnect verification across IP and full-chip integration.

You will design and implement UVM-based testbenches, collaborate with Architecture, SW/FW, Design, and Validation teams, and drive verification strategies for high-performance interconnect subsystems.

Qualifications

• Requires a B.S./M.S. in Computer or Electrical Engineering or equivalent.
• 5+ years in ASIC verification with fabric/interconnect focus at IP and SoC levels.
• Strong SystemVerilog and UVM knowledge.
• Experience with interconnect protocols and NoC architectures.

Responsibilities

• Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and implement test plans for fabric and interconnect verification of SoCs using UVM-based environments, targeting both IP-level and system-level scenarios.
• Design and implement constrained-random and directed SystemVerilog testbenches targeting interconnect fabrics, network-on-chip (NoC) topologies, and multi-agent SoC integrations.
• Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.
• Drive the development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

Skills

SystemVerilog

UVM

Python

Perl

TCL

AMBA AXI

CHI

NoC topologies

SoC interconnect verification

Education

Bachelor's/Master's in Computer or Electrical Engineering

Job description

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions! We are looking for special individuals with desire to deliver innovative products. Together, we will build the next generation of life changing custom SOCs! If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be. This role specifically requires a skilled ASIC Verification Engineer with expertise in fabric and interconnect verification, spanning both IP and SoC integration. You will play a key role in verifying the correctness, performance, and compliance of on-chip fabrics and interconnect subsystems — from IP bring-up through full chip integration — ensuring robust and high-performance connectivity across complex SoC designs. This position demands a motivated individual who understands how complex SOCs and IPs are built, has intimate knowledge of client requirements, and comprehends various development cycles. It requires deep knowledge of SystemVerilog and UVM, along with a solid grasp of ASIC verification methodologies.

What You'll Be Doing

• Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and implement test plans for fabric and interconnect verification of SoCs using UVM-based environments, targeting both IP-level and system-level scenarios.
• Design and implement constrained-random and directed SystemVerilog testbenches targeting interconnect fabrics, network-on-chip (NoC) topologies, and multi-agent SoC integrations.
• Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.
• Drive the development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

What We Need To See

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
• 5+ years of experience in ASIC verification, with a strong focus on fabric, interconnect, or network-on-chip verification at both IP and full chip levels.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with industry-standard interconnect and bus protocols (e.g., AMBA AXI, CHI, or equivalent), with solid understanding of ordering, coherency, and flow control semantics.
• Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.
• Proficiency in scripting languages (Python, Perl, TCL).

Ways To Stand Out From The Crowd

• Knowledge of performance verification and bandwidth/latency analysis for interconnect fabrics.
• Exposure to verification IPs for bus protocols, or emulation platforms (e.g., Palladium, Veloce) for full chip fabric validation.
• Experience in GPU or AI accelerator SoC interconnect verification is desirable.
• Experience with formal verification or assertion-based verification (SVA) applied to fabric and protocol properties.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until August 24, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.