Senior ASIC Verification Engineer – High-Speed IO (Equity)

Nvidia Corporation; Westford (MA); On-site; USD 210,000 - 264,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of next-generation High Speed I/O controllers for leading SOCs and GPUs. The role offers impact across consumer graphics, AI, and autonomous systems, with a team spread globally and a focus on pushing the frontiers of computing.

The candidate will verify IP/sub-system levels using DV methodologies (UVM), develop test plans, and work with cross-functional teams to ensure design correctness.

Qualifications

• Bachelor's or Master’s degree in engineering or equivalent experience.
• 5+ years of relevant experience in design verification.
• Experience at Unit/Sub-system/SOC level and expertise in SystemVerilog, UVM.
• Expertise in verification of IP or interconnect protocols (Ethernet, USB, SATA).
• Experience with random stimulus, coverage-driven verification, and assertion-based verification (UVM).
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication and collaboration skills.

Responsibilities

• Verify ASIC design, architecture, golden models, and micro-architecture of HSIO controllers (e.g., Ethernet, NVLink) at IP/sub-system levels using DV methodologies like UVM.
• Build reusable bus functional models, monitors, checkers, and scoreboards following coverage-driven verification.
• Understand design specs, define verification scope, develop test plans, tests, and verification infrastructure to verify design correctness.
• Collaborate with architects, designers, and pre/post-silicon verification teams to complete tasks.

Skills

SystemVerilog

UVM

IP verification

Debugging

Communication

Python

Perl

Education

Bachelor's or Master's in Engineering

Tools

UVM tools

Simulation tools

Job description

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of next-generation High Speed I/O controllers for leading SOCs and GPUs. The role offers impact across consumer graphics, AI, and autonomous systems, with a team spread globally and a focus on pushing the frontiers of computing.

The candidate will verify IP/sub-system levels using DV methodologies (UVM), develop test plans, and work with cross-functional teams to ensure design correctness.